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HM5425161B Series HM5425801B Series HM5425401B Series
256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword x 16-bit x 4-bank/8-Mword x 8-bit x 4-bank/ 16-Mword x 4-bit x 4-bank
E0086H20 (Ver. 2.0) Jan. 23, 2002 Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
Features
* * * * * * * 2.5 V power supply SSTL-2 interface for all inputs and outputs Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max) Data inputs, outputs, and DM are synchronized with DQS 4 banks can operate simultaneously and independently Burst read/write operation Programmable burst length: 2/4/8 Burst read stop capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5425161B, HM5425801B, HM5425401B Series
* Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable CAS latency: 2/2.5 * 8192 refresh cycles: 7.8 s (64 ms/8192 cycles) * 2 variations of refresh Auto refresh Self refresh
Ordering Information
Type No. HM5425161BTT-75A* HM5425161BTT-75B* 2 HM5425161BTT-10* 3 HM5425801BTT-75A* 1 HM5425801BTT-75B* 2 HM5425801BTT-10* 3 HM5425401BTT-75A* 1 HM5425401BTT-75B* 2 HM5425401BTT-10* 3
1
Frequency 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz
CAS latency 2.0 2.5 2.0 2.0 2.5 2.0 2.0 2.5 2.0
Package 400-mill 66-pin plastic TSOP II
Notes: 1. 143 MHz operation at CAS latency = 2.5. 2. 100 MHz operation at CAS latency = 2.0. 3. 125 MHz operation at CAS latency = 2.5.
Data Sheet E0086H20 2
HM5425161B, HM5425801B, HM5425401B Series
Pin Arrangement (HM5425161B)
66-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 NC VCCQ DQSL NC VCC NC DML WE CAS RAS CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSSQ DQSU NC VREF VSS DMU CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
Data Sheet E0086H20 3
HM5425161B, HM5425801B, HM5425401B Series
Pin Description
Pin name A0 to A12 Function Address input Row address BA0, BA1 DQ0 to DQ15 DQSU DQSL CS RAS CAS WE DMU DML CLK CLK CKE VREF VCC VSS VCCQ VSSQ NC Bank select address Data-input/output Upper input and output data strobe Lower input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Upper byte input mask Lower byte input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A12 A0 to A8 Column address
Data Sheet E0086H20 4
HM5425161B, HM5425801B, HM5425401B Series
Pin Arrangement (HM5425801B)
66-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC NC VCCQ NC NC VCC NC NC WE CAS RAS CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC NC VSSQ DQS NC VREF VSS DM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
Data Sheet E0086H20 5
HM5425161B, HM5425801B, HM5425401B Series
Pin Description
Pin name A0 to A12 Function Address input Row address BA0, BA1 DQ0 to DQ7 DQS CS RAS CAS WE DM CLK CLK CKE VREF VCC VSS VCCQ VSSQ NC Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A12 A0 to A9 Column address
Data Sheet E0086H20 6
HM5425161B, HM5425801B, HM5425401B Series
Pin Arrangement (HM5425401B)
66-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC NC VCCQ NC NC VCC NC NC WE CAS RAS CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC NC VSSQ DQS NC VREF VSS DM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
Data Sheet E0086H20 7
HM5425161B, HM5425801B, HM5425401B Series
Pin Description
Pin name A0 to A12 Function Address input Row address BA0, BA1 DQ0 to DQ3 DQS CS RAS CAS WE DM CLK CLK CKE VREF VCC VSS VCCQ VSSQ NC Bank select address Data-input/output Output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A12 A0 to A9, A11 Column address
Data Sheet E0086H20 8
HM5425161B, HM5425801B, HM5425401B Series
Block Diagram
Address (A12, BA0, BA1)
Address register AY0 to AY11 Column address buffer AX0 to AX12 Row address buffer Refresh counter A0 to A12, BA0, BA1 Mode register BA0, BA1 Bank select
Column address counter
Control logic & timing generator
CLK CLK CKE CS RAS CAS WE DM, DMU/DML
Row decoder Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus
Row decoder Column decoder Sense amplifier & I/O bus
Row decoder Column decoder Sense amplifier & I/O bus
Row decoder
Bank 0
Bank 1
Bank 2
Bank 3
*1
*1
*1
*1
Input buffer Output buffer DQS buffer DLL
DQS, DQSU/DQSL
DQ*2 Notes: 1. 8192 row x 512 column x 16 bit: HM5425161B 8192 row x 1024 column x 8 bit: HM5425801B 8192 row x 2048 column x 4 bit: HM5425401B 2. DQ0 to DQ15: HM5425161B DQ0 to DQ7: HM5425801B DQ0 to DQ3: HM5425401B
Data Sheet E0086H20 9
HM5425161B, HM5425801B, HM5425401B Series
Pin Functions (1)
CLK, CLK (input pin): The CLK and the CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the CLK. CS (input pin): When CS is Low, commands and data can be input. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) is loaded via the A0 to the A9 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, autoprecharge function is disabled. BA0/BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the V REF level with proper setup time tIS, by the next CLK rising edge CKE level must be kept with proper hold time tIH.
Data Sheet E0086H20 10
HM5425161B, HM5425801B, HM5425401B Series
Pin Functions (2)
DM, DMU/DML (input pins): DM (the HM5425801B and the HM5425401B), DMU/DML (the HM5425161B) are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMU/DML provide the byte mask function. When DMU/DML = High, the data input at the same timing are masked while the internal burst counter will be count up. DML controls the lower byte (DQ0 to DQ7) and DMU controls the upper byte (DQ8 to DQ15) of write data. DQ0 to DQ15 (input and output pins): Data are input to and output from these pins (the DQ0 to the DQ15; the HM5425161B, the DQ0 to the DQ7; the HM5425801B, the DQ0 to the DQ3; the HM5425401B). DQS, DQSU/DQSL (input and output pin): DQS (the HM5425801B and the HM5425401B), DQSU/DQSL (the HM5425161B) provide the read data strobes (as output) and the write data strobes (as input). DQSL is the lower byte (DQ0 to DQ7) data strobe signal, DQSU is the upper byte (DQ8 to DQ15) data strobe signal. VCC and V CCQ (power supply pins): 2.5 V is applied. (VCC is for the internal circuit and V CCQ is for the output buffer.) VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.)
Data Sheet E0086H20 11
HM5425161B, HM5425801B, HM5425401B Series
Command Operation
Command Truth Table The HM5425161B, the HM5425801B and HM5425401B recognize the following commands specified by the CS, RAS, CAS, WE and address pins. All other combinations than those in the table below are illegal.
CKE Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge Symbol DESL NOP BST READ READA n-1 n H H H H H H H H H H H H H H H H H H H H H H H H H L H H CS H L L L L L L L L L L L L L RAS CAS WE BA1 BA0 AP x H H H H H H L L L L L L L x H H L L L L H H H L L L L x H L H H L L H L L H H L L x x x V V V V V V x x x L L x x x V V V V V V x x x L H x x x L H L H V L H x x L L Address x x x V V V V V x x x x V V
Column address and write command WRIT Write with auto-precharge Row address strobe and bank active Precharge select bank Precharge all bank Refresh WRITA ACTV PRE PALL REF SELF Mode register set MRS EMRS
Notes: 1. H: VIH. L: V IL. x: V IH or VIL. V: Valid address input 2. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least.
Ignore command [DESL]: When CS is High at the cross point of the CLK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP]: As long as this command is input at the cross point of the CLK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST]: This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ]: This command starts a read operation. The start address of the burst read is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA). After the completion of the read operation, the output buffer becomes High-Z.
Data Sheet E0086H20 12
HM5425161B, HM5425801B, HM5425401B Series
Read with auto-precharge [READA]: This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT]: This command starts a write operation. The start address of the burst write is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA). Write with auto-precharge [WRITA]: This command starts a write operation. After completion of the write operation, precharge is automatically executed. Row address strobe and bank activate [ACTV]: This command activates the bank selected by BA0/BA1 and determines a row address (AX0 to AX12). When BA1 = BA0 = Low, bank 0 is activated. When BA1 = High and BA0 = Low, bank 1 is activated. When BA1 = Low and BA0 = High, bank 2 is activated. When BA1 = BA0 = High, bank 3 is activated. Precharge selected bank [PRE]: This command starts a pre-charge operation for the bank selected by BA0/BA1. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS]: The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
Data Sheet E0086H20 13
HM5425161B, HM5425801B, HM5425401B Series
CKE Truth Table
CKE Current state Idle Idle Idle Command Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry (PDEN) n-1 n H H H H Self refresh Self refresh exit (SELFX) L L Power down Power down exit (PDEX) L L H L L L H H H H CS L L L H L H L H RAS L L H x H x H x CAS L L H x H x H x WE H H H x H x H x Address Notes x x x x x x x x 2 2
Notes: 1. H: V IH. L: VIL. x: VIH or VIL. 2. All the banks must be in IDLE before executing this command. 3. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least.
Auto-refresh command [REF]: This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh contoroller. The average refresh cycle is 7.8 s. The output buffer becomes High-Z after auto-refresh start. Precharge has been completed automatically after the auto-refresh. The ACTV or MRS command can be issued tRFC after the last auto-refresh command. Self-refresh entry [SELF]: This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-refresh operation, all ROW addresses are repeated refreshing by the internal refresh contoroller. A self-refresh is terminated by a self-refresh exit command. Power down mode entry [PDEN]: tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Self-refresh exit [SELFX]: This command is executed to exit from self-refresh mode. 10 cycles (= tSNR ) after [SELFX], non-read commands can be executed. For read operation, wait for 200 cycles (= tSRD ) after [SELFX] to adjust Dout timing by DLL. After the exit, within 7.8 s input auto-refresh command. Power down exit [PDEX]: The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Data Sheet E0086H20 14
HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Function Truth Table (1)
Current state Precharging*
2
CS H L L L L L L L
RAS CAS WE x H H H H L L L x H H H H L L L L x H H H L x H H L L H H L x H H L L H H L L x H H L x x H L H L H L x x H L H L H L H L x H L x x
Address x x x
Command DESL NOP BST
Operation NOP NOP ILLEGAL*
12 12 12 12
Next state ldle ldle -- -- -- -- ldle -- ldle ldle
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x x x x DESL NOP BST ACTV PRE, PALL
ILLEGAL*
ILLEGAL* ILLEGAL* NOP ILLEGAL NOP NOP ILLEGAL*
Idle*
3
H L L L L L L L L
12 12 12
-- -- -- Active ldle ldle/ Selfrefresh
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x MODE x x x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
ILLEGAL*
ILLEGAL* Activating NOP
Refresh/ Selfrefresh*13
Mode register set*13 ldle NOP NOP ILLEGAL ILLEGAL ILLEGAL ldle ldle -- -- --
Refresh (auto-refresh)*4
H L H L L
Data Sheet E0086H20 15
HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table (2)
Current state Activating*
5
CS H L L L L L L L
RAS CAS WE x H H H H L L L x H H H H x H H L L H H L x H H L L x H L H L H L x x H L H L
Address x x x
Command DESL NOP BST
Operation NOP NOP ILLEGAL*
12 12 12 12 12
Next state Active Active -- -- -- -- -- -- Active Active Active Read/READ A Write recovering/ precharging -- Idle -- Active Active Active Active
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x x x x DESL NOP BST ACTV PRE, PALL
ILLEGAL*
ILLEGAL* ILLEGAL*
ILLEGAL* ILLEGAL NOP NOP ILLEGAL
Active*
6
H L L L L
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA
Starting read operation Starting write operation ILLEGAL*12 Pre-charge ILLEGAL
L L L Read*
7
L L L x H H H
H H L x H H L
H L x x H L H
BA, RA BA, A10 x x x x
ACTV PRE, PALL
H L L L
DESL NOP BST
NOP NOP BST Interrupting burst read operation to start new read ILLEGAL*14 ILLEGAL*
12
BA, CA, A10 READ/READA
L L L
H L L
L H H
L H L
BA, CA, A10 WRIT/WRITA BA, RA BA, A10 ACTV PRE, PALL
-- -- Precharging
Interrupting burst read operation to start pre-charge ILLEGAL
L
L
L
x
x
--
Data Sheet E0086H20 16
HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table (3)
Current state CS RAS CAS WE x H H H H L L L x H H H x H H L L H H L x H H L x H L H L H L x x H L H Address x x x Command DESL NOP BST Operation NOP NOP ILLEGAL*
15 15 15 12, 15 12, 15
Next state Precharging Precharging -- -- -- -- -- -- Write recovering Write recovering --
Read with auto- H pre-charge*8 L L L L L L L Write*
9
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x x x x DESL NOP BST ACTV PRE, PALL
ILLEGAL*
ILLEGAL* ILLEGAL*
ILLEGAL* ILLEGAL NOP NOP ILLEGAL
H L L L
BA, CA, A10 READ/READA
L
H
L
L
BA, CA, A10 WRIT/WRITA
L L
L L
H H
H L
BA, RA BA, A10
ACTV PRE, PALL
Interrupting burst Read/ReadA write operation to start read operation. Write/WriteA Interrupting burst write operation to start new write operation. ILLEGAL*12 -- Interrupting write operation to start pre-charge. ILLEGAL Idle
L Write recovering* 10 H L L L L L L L
L x H H H H L L L
L x H H L L H H L
x x H L H L H L x
x x x x DESL NOP BST
-- Active Active -- Read/ReadA Write/WriteA -- -- --
NOP NOP ILLEGAL Starting read operation. Starting new write operation. ILLEGAL*12 ILLEGAL* ILLEGAL
12
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x ACTV PRE/PALL
Data Sheet E0086H20 17
HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table (4)
Current state CS RAS CAS WE x H H H H L L L x H H L L H H L x H L H L H L x Address x x x Command DESL NOP BST Operation NOP NOP ILLEGAL ILLEGAL*
15 15 12, 15 12, 15
Next state Precharging Precharging -- -- -- -- -- --
Write with auto- H pre-charge*11 L L L L L L L Notes: 1. 2. 3. 4. 5. 6. 7.
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x ACTV PRE, PALL
ILLEGAL* ILLEGAL*
ILLEGAL* ILLEGAL
H: VIH. L: V IL. x: VIH or VIL. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reachs "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACTV command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 9. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 10. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 11. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 12. This command may be issued for other banks, depending on the state of the banks. 13. All banks must be in "IDLE". 14. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 15. See `Read with Auto-Precharge Enabled, Write with Auto-Precharge Enable' section.
Data Sheet E0086H20 18
HM5425161B, HM5425801B, HM5425401B Series
Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled The Elpida HM5425401/801/161B series support the concurrent auto precharge feature, a read with autoprecharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided.)
The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below. From command Read w/AP To command (different bank, noninterrupting command) Read or Read w/AP Write or Write w/AP Precharge or Activate Write w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/2) 1 1 + (BL/2) + tWTR BL/2 1 Units tCK tCK tCK tCK tCK tCK
Data Sheet E0086H20 19
HM5425161B, HM5425801B, HM5425401B Series
Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKEH CKEL ACTIVE CKEL CKEH ROW ACTIVE IDLE POWER DOWN
ACTIVE POWER DOWN
BST READ
WRITE Write WRITE WITH AP WRITE READ READ WITH AP READ WITH AP
Read
READ
WRITE WITH AP
READ WITH AP
PRECHARGE WRITEA PRECHARGE PRECHARGE READA
POWER APPLIED
POWER ON
PRECHARGE PRECHARGE
Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Data Sheet E0086H20 20
HM5425161B, HM5425801B, HM5425401B Series
Operation of the DDR SDRAM
Power-up Sequence The following sequence is recommended for Power-up. (1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined). Apply VCC before or at the same time as VCCQ. Apply VCCQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 s. (3) After the minimum 200 s of stable power and clock (CLK, CLK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device.*1 (8) Issue 2 or more auto-refresh commands.*1 (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL. Note: 1. Sequence of (7) and (8) may be reversed. Power-up Sequence after CKE Goes High
(4)
Command PALL
(5)
EMRS
(6)
MRS 2 cycles (min)
(7)
PALL 2 cycles (min) tRP
(8)
REF REF tRC REF tRC
(9)
MRS
Any command
2 cycles (min)
2 cycles (min)
DLL enable
DLL reset with A8 = High 200 cycles (min)
Disable DLL reset with A8 = Low
Data Sheet E0086H20 21
HM5425161B, HM5425801B, HM5425401B Series
Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters are shown in the table bellow are allowed to input to the registers. Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
BA0 BA1 A12 0 MRS 0 0
A11 A10 A9 0 0 0
A8 DR
A7 0
A6
A5
A4
A3 BT
A2
A1 BL
A0
LMODE
A8 DLL Reset A6 A5 A4 CAS Latency 2 010 0 No 1 Yes 1 1 0 2.5
A3 Burst Type 0 Sequential 1 Interleave
A2 A1 A0 0 0 0 0 1 1 1 0 1
Burst Length BT=0 BT=1 2 2 4 8 4 8
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0)
BA0 BA1 A12 A11 A10 A9 1 0 0 0 0 0
A8 0
A7 0
A6 0
A5 0
A4 0
A3 0
A2 0
A1 0
A0 DLL
EMRS A0 DLL Control 0 DLL Enable 1 DLL Disable
Data Sheet E0086H20 22
HM5425161B, HM5425801B, HM5425401B Series
Burst Operation The burst type (BT) and the first three bits of the column address determines the order of a data out.
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Data Sheet E0086H20 23
HM5425161B, HM5425801B, HM5425401B Series
Read/Write Operations
Bank active: A read or a write operation begins with the bank active command [ACTV]. The bank active command determines a bank address (BA0, BA1) and a row address (AX0 to AX12). For the bank and the row, a read or a write command can be issued t RCD after the ACTV is issued.
Read operation: The burst length (BL), the CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command which can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (BA0, BA1) which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL (2 or 2.5) and tAC . The read burst start CL * t CK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS or DQSU/DQSL simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS or the DQSU/DQSL are driven Low from V TT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble. Read Operation (Burst Length)
t0 t1
CLK CLK
Command
Address
DQS* Dout
DQS*:DQS,DUSU/DQSL
24
; ;;
t2 t3 t4 t5 t6 t7 t8 tRCD NOP ACTV NOP READ NOP Row Column tRPRE BL = 2 D0 D1 tRPST BL = 4 D0 D1 D2 D3 BL = 8 D0 D1 D2 D3 D4 D5 D6 D7 CAS latency = 2 BL: Burst length
;
Data Sheet E0086H20
HM5425161B, HM5425801B, HM5425401B Series
Read Operation (CAS Latency)
t0 CLK CLK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
Read tRPRE
NOP tRPST
DQS CL = 2 DQ tRPRE DQS CL = 2.5 DQ tAC,tDQSCK D0 D1 D2 D3 tAC,tDQSCK D0 D1 D2 D3 tRPST
VTT VTT VTT VTT
Data Sheet E0086H20 25
;;;; ;
HM5425161B, HM5425801B, HM5425401B Series
Write operation: The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (BA0/BA1) which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS, DQSU/DQSL should be input as the strobe for the input-data and DM, DMU/DML as well during burst operation. t WPREH prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as wrtie postamble. Write Operation
t0 t1 t2 t3 t3.5 t4 t5 t6 t7 t8 CLK CLK tRCD Command NOP ACTV NOP WRITE NOP Address
; ;
Row Column tWPREH
tWPRES BL = 2 in0 in1 DQS* Din tWPST BL = 4 in0 in1 in2 in3 BL = 8 in0 in1 in2 in3 in4 in5 in6 in7 DQS*:DQS,DQSU/DQSL BL: Burst length
Data Sheet E0086H20
26
HM5425161B, HM5425801B, HM5425401B Series
Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. Burst Stop during a Read Operation
t0 CLK CLK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
Read
BST tBSTZ
NOP 2 cycles
DQS CL = 2 DQ D0 tBSTZ DQS CL = 2.5 DQ D0 D1 CL: CAS latency D1 2.5 cycles
Data Sheet E0086H20 27
HM5425161B, HM5425801B, HM5425401B Series
Auto Precharge Read with auto-precharge: The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. A column command to the other active bank can be issued at the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to the `Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled' section.
CLK CLK tRP (min)
tRAP (min) = tRCD (min)
tRPD 2 cycles (= BL/2) NOP ACTV
Command DQS, DQSU/DQSL DQ
ACTV
READA
tAC,tDQSCK
D0
D1
D2
D3
Note: Internal auto-precharge starts at the timing indicated by "
".
Data Sheet E0086H20 28
Write with auto-precharge: The precharge is automatically performed after completing a burst write operation. The precharge operation is started tWPD (= BL/ 2 + 3) cycles after WRITA command issued. tRCD for WRITA should be determined so that tRC (ACTV to ACTV) spec. is obeyed when WRITA is issued successively after a bank active command, that is tRCD (WRITA) tRC(min.)-tRP(min.)-tWPD . A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Refer to the `Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled' section Burst Write (Burst Length = 4)
CLK CLK
Command
DM, DMU/DML DQS, DQSU/DQSL DQ
Note: Internal auto-precharge starts at the timing indicated by "
;;; ;
HM5425161B, HM5425801B, HM5425401B Series
tRAS (min) tRP tRCD (min) NOP ACTV WRITA NOP ACTV tWPD BL/2 + 3 cycles D1 D2 D3 D4 ".
Burst length = 4
Data Sheet E0086H20
29
; ;; ;
HM5425161B, HM5425801B, HM5425401B Series
Command Intervals A Read command to the consecutive Read command Interval
Destination row of the consecutive read command Bank address Row address Same State Operation 1. Same 2. Same ACTIVE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Different -- Precharge the bank to interrupt the preceding read operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. 3. Different Any ACTIVE IDLE Precharge the bank without interrupting the preceding read operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued.
READ to READ Command Interval (same ROW address in the same bank)
t0 t1 t2 t3 t4 t5 t6
t7
t8
CLK CLK
Command
ACTV
NOP
READ
READ
NOP
Address BA
Row
Column A Column B
Dout
A0
A1
B0
B1
B2
B3
Column = A Read
Column = B Read
Column = A Dout
Column = B Dout
DQS, DQSU/DQSL
Bank0 Active
CAS latency = 2 Burst length = 4 Bank0
Data Sheet E0086H20
30
; ;; ;
HM5425161B, HM5425801B, HM5425401B Series
READ to READ Command Interval (different bank)
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 CLK CLK Command ACTV NOP ACTV NOP READ READ NOP Address BA Row0 Row1 Column A Column B Dout A0 A1 B0 B1 B2 B3
Column = A Column = B Read Read
Bank0 Dout
Bank3 Dout
DQS, DQSU/DQSL
Bank0 Active
Bank3 Active
Bank0 Read
Bank3 Read
CAS latency = 2 Burst length = 4
Data Sheet E0086H20
31
HM5425161B, HM5425801B, HM5425401B Series
A Write command to the consecutive Write command Interval:
Destination row of the consecutive write command Bank address 1. Same 2. Same Row address Same State
3. Different
WRITE to WRITE Command Interval (same ROW address in the same bank)
t0 t1 t2 t3 t4 t5 t6 t7
DQS, DQSU/DQSL
32
;; ;; ;
Operation ACTIVE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Different -- Precharge the bank to interrupt the preceding write operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive write command can be issued. See `A write command to the consecutive precharge interval' section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Any ACTIVE IDLE Precharge the bank without interrupting the preceding write operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive write command can be issued.
t8 CLK CLK Command ACTV NOP WRIT WRIT NOP Address BA Row Column A Column B Din A0 A1 B0 B1 B2 B3 Column = A Write Column = B Write Bank0 Active Burst length = 4 Bank0
Data Sheet E0086H20
;;; ;;
HM5425161B, HM5425801B, HM5425401B Series
WRITE to WRITE Command Interval (different bank)
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 CLK CLK Command ACTV NOP ACTV WRIT WRIT NOP Address BA Row0 Row1 Column A Column B Din A0 A1 B0 B1 B2 B3 Bank0 Write Bank3 Write DQS, DQSU/DQSL Bank0 Active Bank3 Active Burst length = 4 Bank0, 3
Data Sheet E0086H20
33
HM5425161B, HM5425801B, HM5425401B Series
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write command Bank address 1. Same 2. Same Row address Same Different State ACTIVE -- Operation Issue the BST command. t BSTW ( tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive write command can be issued. See `A read command to the consecutive precharge interval' section. Issue the BST command. t BSTW ( tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive write command can be issued.
3. Different
Any
ACTIVE IDLE
READ to WRITE Command Interval
t0 CLK CLK t1 t2 t3 t4 t5 t6 t7 t8
Command
READ
BST
NOP tBSTW ( tBSTZ)
WRIT
NOP
DM, DMU/DML tBSTZ (= CL) DQ High-Z DQS, DQSU/DQSL OUTPUT INPUT Burst Length = 4 CAS Latency= 2
Q0
Q1
D0
D1
D2
D3
Data Sheet E0086H20 34
HM5425161B, HM5425801B, HM5425401B Series
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read command Bank address 1. Same 2. Same Row address Same Different State ACTIVE --
Operation
To complete the burst operation, the consecutive read command should be performed t WRD (= BL/ 2 + 2) after the write command.
Precharge the bank t WPD after the preceding write command. tRP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section.
3. Different
Any
ACTIVE IDLE
To complete a burst operation, the consecutive read command should be performed t WRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued.
WRITE to READ Command Interval
t0 CLK CLK t1 t2
Command
WRIT
NOP
tWRD (min) DM, DMU/DML
BL/2 + 2 cycle
DQ
D0
D1
D2
DQS, DQSU/DQSL INPUT
Data Sheet E0086H20
;; ;
t3 t4 t5 t6 READ NOP D3 Q0 Q1 Q2 OUTPUT BL = 4 CL = 2
35
HM5425161B, HM5425801B, HM5425401B Series
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read command Bank address 1. Same Row address Same State ACTIVE Operation DM, DMU/DML must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM, DMU/DML is not necessary. --* 1 DM, DMU/DML must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM, DMU/DML is not necessary. --* 1
2. Same 3. Different
Different Any
-- ACTIVE
IDLE Note:
1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case.
WRITE to READ Command Interval (Samebank, same ROW address) [WRITE to READ delay = 1 clock cycle]
t0 CLK CLK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
READ CL=2
NOP
1 cycle
DM, DMU/DML
DQ
D0
D1
D2
Q0
Q1 Q2
Q3
High-Z High-Z
DQS, DQSU/DQSL Data masked BL = 4 CL= 2
Data Sheet E0086H20 36
HM5425161B, HM5425801B, HM5425401B Series
[WRITE to READ delay = 2 clock cycle]
t0 CLK CLK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP 2 cycle
READ CL=2
NOP
DM, DMU/DML High-Z High-Z DQS, DQSU/DQSL Data masked BL = 4 CL= 2
DQ
D0
D1
D2
D3
Q0
Q1 Q2
Q3
[WRITE to READ delay = 3 clock cycle]
t0 CLK CLK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP 3 cycle
READ CL=2
NOP
DM, DMU/DML DQ
D0
D1
D2
D3
Q0
Q1 Q2
Q3
DQS, DQSU/DQSL Data masked BL = 4 CL= 2
Data Sheet E0086H20 37
HM5425161B, HM5425801B, HM5425401B Series
A Read command to the consecutive Precharge command interval (same bank): To output all data: To complete a burst read opeartion and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4
t0 CLK CLK Command NOP NOP
PRE/ PALL
t1
t2
t3
t4
t5
t6
t7
t8
READ
NOP
Dout
A0
A1
A2
A3
DQS, DQSU/DQSL tRPD = BL/2
CAS Latency = 2.5, Burst Length = 4
t0 CLK CLK Command NOP NOP
PRE/ PALL
t1
t2
t3
t4
t5
t6
t7
t8
READ
NOP
Dout
A0
A1
A2
A3
DQS, DQSU/DQSL tRPD = BL/2
Data Sheet E0086H20 38
HM5425161B, HM5425801B, HM5425401B Series
READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become HighZ tHZP (= CL) after the precharge command. CAS Latency = 2, Burst Length = 2, 4, 8
t0 CLK CLK Command NOP READ
PRE/PALL
t1
t2
t3
t4
t5
t6
t7
t8
NOP High-Z A0 A1 High-Z
Dout DQS, DQSU/DQSL
tHZP = CL + 1
CAS Latency = 2.5, Burst Length = 2, 4, 8
t0 CLK CLK Command NOP READ PRE/PALL CL = 2.5 Dout DQS, DQSU/DQSL tHZP = CL + 1 A0 A1 High-Z NOP High-Z t1 t2 t3 t4 t5 t6 t7 t8
Data Sheet E0086H20 39
HM5425161B, HM5425801B, HM5425401B Series
A Write command to the consecutive Precharge command interval (same bank): The minimum interval tWPD ((BL/ 2 + 3) cycles) is necessary between the write command and the precharge command. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4
Command
DM, DMU/DML DQS, DQSU/DQSL Din
40
;;;;;
t0 t1 t2 t3 t4 t5 t6 t7 CLK CLK WRIT NOP
PRE/PALL
NOP
tWPD
BL/2 +3 cycles
tWR
A0
A1
A2
A3
Last data input
Data Sheet E0086H20
Bank active command interval:
Destination row of the consecutive ACTV command Bank address 1. Same Row address Any State
2. Different
Bank Active to Bank Active
Command
Address
Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tMRD .
CLK CLK
;;;; ;
HM5425161B, HM5425801B, HM5425401B Series
Operation ACTIVE Two successive ACTV commands can be issued at t RC interval. In between two successive ACTV operations, precharge command should be executed. Any ACTIVE Prechage the bank. t RP after the precharge command, the consecutive ACTV command can be issued. IDLE t RRD after an ACTV command, the next ACTV command can be issued. CLK CLK ACTV ACTV ACTV NOP PRE NOP ACTV NOP ROW: 0 ROW: 1 ROW: 0 BA Bank0 Active tRRD Bank3 Active Bank0 Precharge Bank0 Active tRC Command MRS NOP ACTV NOP Address CODE BS and ROW Bank3 Active Mode Register Set tMRD Data Sheet E0086H20 41
;; ;
HM5425161B, HM5425801B, HM5425401B Series
DMU/DML Control (HM5425161B) DMU can mask upper byte of input data. DML can mask lower byte of input data. By setting DMU/DML to Low, data can be written. When DMU/DML is set to High, the corresponding data is not written, and the previous data is held. The latency between DMU/DML input and enabling/disabling mask function is 0. DM Control (HM5425801B/HM5425401B) DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1 DQS, DQSU/DQSL t2 t3 t4 t5 t6
DQ
Mask
Mask
DM, DMU/DML Write mask latency = 0
Data Sheet E0086H20 42
HM5425161B, HM5425801B, HM5425401B Series
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on inputs pin relative to Vss Voltage on I/O pins relative to V SS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VCC, VCCQ Vti VTio Iout PT Topr Tstg Value -1.0 to +3.6 -1.0 to +3.6 -0.5 to +3.6 50 1.0 0 to +70 -55 to +125 Unit V V V mA W C C Note
DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC, VCCQ VSS , VSSQ Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage (CLK, /CLK) DC differential input voltage (CLK, /CLK) Notes: 1. 2. 3. 4. 5. 6. 7. 8. VREF(DC) VTT VIH(DC) VIL(DC) VIN (DC) VID (DC) Min 2.3 0 0.5xVCCQ-0.05 VREF- 0.04 VREF+0.15 -0.3 -0.3 0.36 Typ 2.5 0 0.5xVCCQ VREF -- -- -- -- Max 2.7 0 0.5xVCCQ+0.05 VREF+0.04 VCCQ+0.3 VREF-0.15 VCCQ + 0.3 VCCQ + 0.6 Unit V V V V V V V V 1 1 1, 3, 8 1, 4, 8 5 6, 7 Notes 1, 2
All parameters are referred to VSS , when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 3.6 V for the period shorter than or equal to 5 ns. VIL is allowed to outreach below VSS down to -1.0 V for the period shorter than or equal to 5 ns. VIN (dc) specifies the allowable dc execution of each differential input. VID (dc) specifies the input differential voltage required for switching. VIH (CLK) min assumed over V REF + 0.15 V, VIL(CLK) max assumed under VREF - 0.15 V. VIH (DC) and VIL (DC) are levels to maintain the current logic state.
Data Sheet E0086H20 43
HM5425161B, HM5425801B, HM5425401B Series
DC Characteristics 1 (Ta = 0 to +70C, VCC, VCCQ = 2.5 V 0.2 V, V SS, VSSQ = 0 V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol I LI I LO VOH VOL Min -2 -5 1.95 -- Max 2 5 -- 0.35 Unit A A V V Test conditions VCC Vin V SS VCCQ Vout V SSQ I OH (max) = -15.2 mA I OL (min) = 15.2 mA Notes
Data Sheet E0086H20 44
HM5425161B, HM5425801B, HM5425401B Series
Data Driver Output Characteristic Curves
1. The full variation in driver pulldown current from minimum to maximum temperature and voltage will lie within the outer bounding lines of the V-I curve of the figure "Pull-down Characteristics".
150
Maximum
Pulldown Current (mA)
125
Typical High
100 75 50
Typical Low
Minimum
25 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
VOUT to VSSQ (V)
Pull-down Characteristics 2. The full variation in driver pullup current from minimum to maximum temperature and voltage will lie within the outer bounding lines of the V-I curve of the figure "Pull-up Characteristics".
0 -25
Minimum
Pullup Current (mA)
-50 -75 -100 -125 -150 -175 -200 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Typical Low Typical High
Maximum
2.2 2.4 2.6 2.8
VDDQ to VOUT (V)
Pull-up Characteristics 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the typical IBIS pullup to typical IBIS pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. 7. These characteristics obey the SSTL_2 class II standard.
Data Sheet E0086H20 45
HM5425161B, HM5425801B, HM5425401B Series
Data Driver Output Characteristic V-I data points
Evaluation Conditions * Typical: Ta = 25C, VCCQ = 2.5 V * Minimum: Ta = 70C, VCCQ = 2.3 V * Maximum: Ta = 0C, VCCQ = 2.7 V
Pull-down current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Minimum 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Maximum 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Pull-up current (mA) Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Minimum -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Maximum -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Data Sheet E0086H20 46
HM5425161B, HM5425801B, HM5425401B Series
DC Characteristics 2*1 (Ta = 0 to +70C, VCC, VCCQ = 2.5 V 0.2 V, V SS, VSSQ = 0 V)
Max Parameter Symbol I/O -75A 100 155 18 40 25 50 x 4, x 8 x 16 x 4, x 8 x 16 225 255 205 240 205 3 x 4, x 8 x 16 330 360 -75B 95 145 15 35 20 45 215 245 195 230 200 3 320 350 -10 80 130 12 30 15 40 205 235 185 220 180 3 310 340 Unit mA mA mA mA mA mA mA mA mA mA mA
Operating current (ACTV- I CC0 PRE) Operating current (ACTV- I CC1 READ-PRE) Idle power down standby I CC2P current Idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto Refresh current Self refresh current Random read current I CC2N I CC3P I CC3N I CC4R I CC4W I CC5 I CC6 I CC7A
Notes: 1. These ICC data are measured under condition that DQ pins are not connected.
Data Sheet E0086H20 47
HM5425161B, HM5425801B, HM5425401B Series
ICC Measurement Condition
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Idle standby current Symbol I CC0 Condition One Bank ; CKE VIH(min), tRC = tRC (min); tCK = tCK (min); DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One Bank; CKE VIH(min); Burst = 2; tRC = tRC (min); CL = 2.5; tCK = tCK (min); Iout = 0 mA; address and control inputs changing once per clock cycle All banks idle; power down mode; CKE VIL(max); tCK = tCK (min). Vin = VREF for DQ, DQS and DM All banks idle; CS VIH (min); CKE VIH (min); tCK = tCK (min); Address and other control inputs changing once per clock cycle. Vin VIH(min) or Vin VIL(max) for DQ, DQS and DM. One bank active; power down mode; CKE VIL (max); tCK = tCK (min) One bank; Active Precharge; CS VIH (min); CKE VIH (min); tRC = t RAS (max); tCK = tCK (min); DQ,DM and DQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle One bank active ; CKE VIH(min); Burst = 2; Reads; Continuous burst; address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK (min); Iout = 0 mA; One bank active; CKE VIH(min); Burst = 2; Writes; Continuous burst; address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK (min); DQ, DM and DQS inputs changing twice per clock cycle t RC = tRFC (min); Vin VIL(max) or VIH(min) CKE 0.2 V, Vin 0.2V or VCCQ-0.2V 4 banks active read with activate every 2 clocks, AP (Auto Precharge) read every 2 clocks, BL = 4, tRCD =3, Iout = 0 mA, 100% DQ, DM and DQS inputs changing twice per clock cycle; 100% addresses changing once per clock cycle.
I CC1
I CC2P I CC2N
Active power down standby current Active standby current
I CC3P I CC3N
Operating current (Burst read operation) Operating current (Burst write operation)
I CC4R
I CC4W
Auto refresh current Self refresh current Random read current
I CC5 I CC6 I CC7A
Data Sheet E0086H20 48
HM5425161B, HM5425801B, HM5425401B Series
Capacitance (Ta = 25C, VCC, VCCQ = 2.5 V 0.2 V)
Parameter Input capacitance (CLK, CLK) Symbol CI1 Min 2 2 4 Max 3 3 5 0.5 0.25 Unit pF pF pF pF pF Notes 1 1 1, 2 1 1
Input capacitance (input only pins; including CKE CI2 but not including CLK, CLK) Input/output capacitance (DQ, DM, DQS) Delta input /output capacitance (DQ, DM, DQS) Delta input capacitance (CLK, CLK only) CIO CIOD CID
Notes: 1. These parameters are measured on conditions: f = 100 MHz, Vout = V CCQ/2, Vout = 0.2 V. 2. Dout circuits are disabled.
Data Sheet E0086H20 49
HM5425161B, HM5425801B, HM5425401B Series
AC Characteristics (Ta = 0 to +70C, VCC, VCCQ = 2.5 V 0.2 V, V SS, VSSQ = 0 V)
HM5425161B/HM542581B/HM5425401B -75A Parameter Clock cycle time (CAS latency = 2) (CAS latency = 2.5) Input clock high level time Input clock low level time CLK half period CLK to DQS skew DATA to CLK skew Dout to DQS skew DQ/DQS output skew hold time Data hold skew factor Dout/DQS valid window DQS valid window DQS read preamble DQS read postamble Symbol Min t CK t CK t CH t CL t HP t DQSCK t AC t DQSQ t QH t QHS t DV t DQSV t RPRE t RPST 7.5 7 0.45 0.45 Max 12 12 0.55 0.55 -75B Min 10 7.5 0.45 0.45 Max 12 12 0.55 0.55 -10 Min 10 8 0.45 0.45 Max 12 12 0.55 0.55 Unit Notes ns ns t CK t CK t CK ns ns ns t CK ns t CK t CK t CK t CK ns ns ns ns ns ns t CK t CK 9 5, 11 6, 11 7 8 8 2, 11 2, 11 3 10
min -- (tCH, tCL) -0.75 -0.75 -- 0.75 0.75 0.5
min -- (tCH, tCL) -0.75 -0.75 -- 0.75 0.75 0.5
min -- (tCH, tCL) -0.8 -0.8 -- 0.8 0.8 0.6
t HP - t QHS -- -- 0.35 0.35 0.9 0.4 -0.75 -0.75 1.75 0.5 0.5 0 0.25 0.4 0.75 -- -- 1.1 0.6 0.75 0.75 -- -- -- -- -- 0.6
t HP - t QHS -- -- 0.35 0.35 0.9 0.4 -0.75 -0.75 1.75 0.5 0.5 0 0.25 0.4 0.75 -- -- 1.1 0.6 0.75 0.75 -- -- -- -- -- 0.6
t HP - t QHS -- -- 0.35 0.35 0.9 0.4 -0.8 -0.8 2 0.6 0.6 0 0.25 0.4 1.0 -- -- 1.1 0.6 0.8 0.8 -- -- -- -- -- 0.6
Dout-High impedance delay t HZ from CLK/CLK Dout-Low impedance delay t LZ from CLK/CLK DQ and DM input pulse width t DIPW
Data and data mask to data t DS strobe setup time Data and data mask to data t DH strobe hold time Clock to DQS write preamble setup time Clock to DQS write preamble hold time t WPRES t WPREH
DQS last edge to High-Z t WPST time (DQS write postamble)
Data Sheet E0086H20 50
HM5425161B, HM5425801B, HM5425401B Series
HM5425161B/HM5425801B/HM5425401B -75A Parameter Clock to the DQS first rising edge for write delay Symbol Min t DQSS 0.72 0.2 0.2 0.35 0.35 0.9 0.9 20 65 75 45 20 15 35 20 15 -- Max 1.28 -- -- -- -- -- -- -- -- -- -75B Min 0.72 0.2 0.2 0.35 0.35 0.9 0.9 20 65 75 Max 1.28 -- -- -- -- -- -- -- -- -- -10 Min 0.75 0.2 0.2 0.35 0.35 1.1 1.1 20 70 80 Max 1.25 -- -- -- -- -- -- -- -- -- Unit Notes t CK t CK t CK t CK t CK ns ns ns ns ns 8 8
DQS falling edge to CLK setup t DSS time DQS falling edge hold time to CLK DQS high pulse width (DQS write) DQS low pulse width (DQS write) Input command and address setup time Input command and address hold time RAS to READ (with auto precharge) Active command period Auto refresh to active/Auto refresh command cycle t DSH t DQSH t DQSL t IS t IH t RAP t RC t RFC
Active to Precharge command t RAS period Active to column command period Write recovery time t RCD t WR
120000 45 -- -- -- -- -- 7.8 20 15 35 20 15 --
120000 50 -- -- -- -- -- 7.8 20 15 40 20 15 --
120000 ns -- -- -- -- -- 7.8 ns ns ns ns ns s
Auto precharge write recovery t DAL and precharge time Precharge to active command t RP period Active to active command period Average periodic refresh interval t RRD t REF
Data Sheet E0086H20 51
HM5425161B, HM5425801B, HM5425401B Series
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see `Timing Waveforms' section. 2. This parameter defines the signal transition delay from the cross point of CLK and CLK. The signal transition is defined to occur when the signal level crossing V TT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing V TT. 5. t HZ is defined as Dout transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CLK and CLK. This parameter is not referred to a specific Dout voltage level, but specify when the device output stops driving. 6. t LZ is defined as Dout transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific Dout voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing V REF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. t CK max is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. t CK = min when these parameters are measured. Otherwise, absolute minimum value of these values are 10% of tCK. 12. VCC is assumed to be 2.5 V 0.2 V. VCC power supply variation per cycle expected to be less than 0.4 V/400 cycle.
Data Sheet E0086H20 52
HM5425161B, HM5425801B, HM5425401B Series
Test Conditions
Parameter Input reference voltage Termination voltage AC input high voltage AC input low voltage Symbol VREF(AC) VTT (AC) VIH (AC) VIL (AC) Min 0.5xVCCQ-0.05 VREF(AC) - 0.04 VREF (AC) + 0.31 -- 0.7 0.5 x V CCQ - 0.2 -- Typ 0.5 x V CCQ VREF(AC) -- -- -- 0.5 x V CCQ 1 Max 0.5xVCCQ+0.05 Unit V
VREF (AC) + 0.04 V -- V VREF (AC) - 0.31 V VCCQ + 0.6 V
AC differential input voltage (CLK, VID (AC) CLK) AC differential cross point voltage VX (AC) (CLK, CLK) Input signal slew rate SLEW
0.5 x V CCQ + 0.2 V -- V/ns
tCK CLK CLK VID(AC) tCL tCH
VCC VREF (AC) VX(AC) VSS
VCC VIH VIL t VREF VSS
SLEW = (VIH (AC) - VIL (AC))/t
VTT Measurement point DQ CL = 30 pF RT = 50
Data Sheet E0086H20 53
HM5425161B, HM5425801B, HM5425401B Series
Timing Parameter Measured in Clock Cycle
Number of clock cycle Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CAS latency = 2) (CAS latency = 2.5) Burst stop command to DQ High-Z (CAS latency = 2) (CAS latency = 2.5) Symbol t WPD t RPD t WRD t BSTW t BSTW t BSTZ t BSTZ Min 3 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 3 + BL/2 2 2.5 1 5 2 0 2 10 200 1 1 1 Max
Read command to write command delay (to output all data) t RWD (CAS latency = 2) (CAS latency = 2.5) Pre-charge command to High-Z (CAS latency = 2) (CAS latency = 2.5) Write command to data in latency Auto precharge write recovery and precharge time Write recovery DM to data in latency Register set command to active or register set command Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input CKE minimum pulse width t RWD t HZP t HZP t WCD t DAL t WR t DMD t MRD t SNR t SRD t PDEN t PDEX t CKEPW
Data Sheet E0086H20 54
Timing Waveforms
Command and Addresses Input Timing Definition
CLK CLK
Read Timing Definition
CLK CLK
DQS
DQ (Dout)
;;;;;
HM5425161B, HM5425801B, HM5425401B Series
Command (RAS, CAS, WE, CS) Address tIS tIH VREF tIS tIH VREF
tCK tCH tCL tDQSCK tDQSCK tDQSCK tDQSCK tDQSCK tDQSCK tRPST tRPRE tDQSQ tLZ tAC tQH tAC tDQSQ tAC tQH tAC tHZ tQH tDQSQ tQH tDQSQ tQH
Data Sheet E0086H20
55
HM5425161B, HM5425801B, HM5425401B Series
Write Timing Definition
tCK CLK CLK
tDQSS
tDSS
tDSH
tDSS VREF
DQS tWPRES tWPREH DQ (Din) tDS DM tDS tDH tDIPW tDIPW tDH tDIPW tDQSL tDQSH tWPST
VREF
VREF
Data Sheet E0086H20 56
HM5425161B, HM5425801B, HM5425401B Series
Read Cycle
tCK tCH tCL
; ; ;; ; ;; ; ;;;;;
CLK CLK VIH tRC CKE tRCD tRAS tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH CS RAS tIS tIH tIS tIH tIS tIH tIS tIH CAS tIS tIH tIS tIH tIS tIH tIS tIH WE tIS tIH tIS tIH tIS tIH tIS tIH BA tIS tIH tIS tIH tIS tIH tIS tIH A10 tIS tIH tIS tIH tIS tIH Address DM, DMU/DML DQS, DQSU/DQSL High-Z tRPRE tDQSVtDQSV tRPST tDV tDV DQ (output) High-Z Bank 0 Active Bank 0 Read Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank0 Access = VIH or VIL
Data Sheet E0086H20 57
;;; ;; ;
HM5425161B, HM5425801B, HM5425401B Series
Write Cycle
tCK tCH tCL CLK CLK VIH tRC CKE tRCD tRAS tRP tIS tIH tIS tIH tIS tIH CS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH RAS tIS tIH tIS tIH tIS tIH tIS tIH CAS tIS tIH tIS tIH tIS tIH tIS tIH WE tIS tIH tIS tIH tIS tIH tIS tIH BA tIS tIH tIS tIH tIS tIH tIS tIH A10 tIS tIH tIS tIH tIS tIH Address tDQSS tDQSL tWPST DQS, DQSU/DQSL (input) tDQSL tDS tDS tDH DM, DMU/DML tDS tDH DQ (input) tWR tDH Bank 0 Active Bank 0 Write Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank0 Access = VIH or VIL
Data Sheet E0086H20
58
;;; ; ;;;; ;
HM5425161B, HM5425801B, HM5425401B Series
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK CKE CS VIH RAS CAS WE BA code Address valid code R: b C: b DM, DMU/DML DQS, DQSU/DQSL
High-Z High-Z
DQ (output)
b
tRP
tMRD
Precharge If needed
Mode register set
Bank 3 Active
Bank 3 Read
Bank 3 Precharge
CAS latency = 2 Burst length = 4 = VIH or VIL
Data Sheet E0086H20
59
HM5425161B, HM5425801B, HM5425401B Series
Read/Write Cycle
;;; ; ;
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS VIH RAS CAS WE BA Address
R:a C:a R:b C:b C:b''
;; ;;
DM, DMU/DML DQS, DQSU/DQSL DQ (output) DQ (input)
a
b''
High-Z
tRWD
b
tWRD
Bank 0 Active
Bank 0 Bank 3 Read Active
Bank 3 Write
Bank 3 Read Read cycle CAS latency = 2 Burst lenght = 4 =VIH or VIL
Data Sheet E0086H20 60
HM5425161B, HM5425801B, HM5425401B Series
Auto Refresh Cycle
CLK CLK CKE CS RAS CAS WE BA Address DM, DMU/DML DQS DQSU/DQSL DQ (output) DQ (input) High-Z tRP Precharge If needed Auto Refresh tRFC Bank 0 Active Bank 0 Read CAS latency = 2 Burst length = 4 = VIH or VIL b
A10=1
VIH
R: b
C: b
Data Sheet E0086H20 61
HM5425161B, HM5425801B, HM5425401B Series
Self Refresh Cycle
CLK CLK CKE CS RAS CAS WE BA Address DM, DMU/DML DQS DQSU/DQSL DQ (output)
High-Z
tIS tCKEPW
tIH
CKE = low
A10=1
R: b
C: b
DQ (input)
tRP Precharge If needed Self refresh entry Self refresh exit
tSNR tSRD Bank 0 Active Bank 0 Read CAS latency = 2.5 Burst length = 4 = VIH or VIL
Data Sheet E0086H20 62
;; ;;;
HM5425161B, HM5425801B, HM5425401B Series
Power Down Mode
CLK CLK
tIS tIH
;;; ;;; ;;; ;; ;;;; ;; ;; ;; ;;; ;
CKE CS
CKE = low
tCKEPW
RAS CAS
WE BA
Address
A10=1
R: b
R: c
DM, DMU/DML QS, QSU/QSL
DQ (output) DQ (input)
High-Z
tRP
Precharge If needed
tPDEN Power down entry
tPDEX Power Bank 0 Bank 0 down Active Read exit CAS latency = 2.5 Burst lenght = 4 =VIH or VIL
Data Sheet E0086H20 63
HM5425161B, HM5425801B, HM5425401B Series
Package Dimensions
HM5425161BTT/HM5425801BTT/HM5425401BTT Series
Unit: mm
22.22 0.10 *1
A
66
34
PIN#1 ID
1
0.65
33
B 0.80 Nom 0 to 8
0.17 to 0.32 0.91 max.
0.13 M S A B
11.76 0.20
10.16
0.25
1.0 0.05
1.20 max
0.09 to 0.20
S
0.10 S
0.10 +0.08 -0.05
0.60 0.15
Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. ECA-TS2-0029-01
Data Sheet E0086H20 64
HM5425161B, HM5425801B, HM5425401B Series
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
(c) Hitachi, Ltd., 2000
Data Sheet E0086H20 65

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